This invention relates to a horizontal position compensation circuit for compensating horizontal position of a picture on a display. When a first video signal which is produced by computer graphics in a host computer and a second video signal which is not produced by computer graphics in the host computer are simultaneously displayed on a raster scanned display, it is necessary to compensate horizontal position of the first video signal on the display, because a video signal produced by computer graphics has different intervals between a horizontal synchronizing pulse and a start point of the video signal for different host computers. Therefore, when an area of a picture of the first video signal is deleted and there a part of a picture of the second video signal is inserted, a gap may be formed between the two pictures when the horizontal position of the first video signal is not compensated.
Heretofore, the horizontal position compensation of the first video signal is performed by an operator through an interactive input unit controlled by a program called a tuning soft. A prior art of the horizontal position compensation is described in connection with FIG. 6 and FIG. 7.
In an example shown in FIG. 6, the host computer is a personal computer(abbreviated to PC), and a first video signal produced by computer graphics in PC proper 1 is denoted by PC-RGB. A second video signal which is not produced by computer graphics in the PC proper 1 is denoted by "VIDEO SIGNAL". A first frame buffer 4 is to store temporally the first video signal, and a second frame buffer 2 is to store temporally the second video signal. A read address counter 3 generates address signal for reading both frame buffers 2 and 4. This address signal is used also for writing the second frame buffer 2. A write address counter 5 generates address signal for writing the first frame buffer 4.
The read address counter 3 and the write address counter 5 are controlled by clock signals from the PC proper 1. The clock signals include dot clocks, horizontal synchronizing pulses, and vertical synchronizing pulses, and are denoted by "CLOCK" in the drawing. These clocks are delayed by a horizontal position compensator 65 and are delivered to the write address counter 5. Thus, the first video signal is stored in the first frame buffer 4 at an address reduced by the delay.
The amount of delay is stored in an EEPROM 64, and at an initialization, the contents of the EEPROM 64 are transferred to a compensation register 63. The contents of the compensation register 63 is changed by an up/down signal delivered by an operator through an interactive input unit(not shown in the drawing).
In an operation mode of the circuit of FIG. 6, the first video signal stored in the first frame buffer 4, and the second video signal stored in the second frame buffer 2 are read out accessed by the output of the read address counter 3. Either one of the two signals read out from the two frame buffers 2 and 4 is selected by a data selector 7 and converted to an analog signal by DAC(a digital analog converter)10 to be displayed on a display 11. The sweep of the display 11 is controlled by the PC proper 1. And the PC proper 1 controls through the data selector 7 an area of the screen of the display 11 wherein the first video signal is substituted by the second video signal.
The first video signal and the second video signal are digital signals, for example, a pixel in the picture is represented by three color intensity values R,G,B, each component being represented by 8 bits of a binary digits. For memory volume economy, there are cases when the three color intensity values R,G,B are converted to Y(8 bits),Cr(4 bits),Cb(4 bits) and are stored in the frame buffers 2 and 4. In these cases a matrix circuit must be inserted between the DAC 10 and the display 11 for converting to three color intensity values R,G,B.
In a compensation mode, a tuning soft 62 in the PC proper 1 executes a program shown in FIG. 7. At an initialization step 101, the contents of the EEPROM 64 are loaded to the compensation register 63. At a step 102, a predetermined dot pattern(hereafter called a second dot pattern) is loaded in the second frame buffer 2 in a predetermined range of address. At a step 103, a first dot pattern is produced by computer graphics in the predetermined range of address, and is loaded in the first frame buffer 4. In a step 104, the two frame buffers 2 and 4 are read out by the read address counter 3. The read out signals are alternately displayed as shown by a step 105 and a step 106. The operator observes the display, and when the first dot pattern picture and the second dot pattern picture do not coincide on the screen of the display 11, he delivers the up/down signal through the interactive input unit to displace the first dot pattern picture horizontally to a place coincident with the second dot pattern picture. And from a command delivered by the operator through the interactive input unit, the contents of the compensation register 63 is stored in the EEPROM 64. In a next operation mode, there is a high probability in which no compensation is necessary, since an adaptive compensation data is stored in the EEPROM 64.
In a prior art method of horizontal position compensation, the step 107 and 108 must be performed by an operator, and this is a troublesome burden on the operator.